Applying Logic Synthesis for Speeding Up SAT Niklas Een, Alan Mishchenko, Niklas S¨ orensson Cadence Berkeley Labs, Berkeley, USA. EECS Department, University of California, Berkeley, USA. Chalmers University of Technol

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Date: 2007-03-20 02:33:25 Theoretical computer science Conjunctive normal form And-inverter graph Science Mathematics Circuit Canonical form Boolean network Logic Electronic design automation Formal methods		Applying Logic Synthesis for Speeding Up SAT Niklas Een, Alan Mishchenko, Niklas S¨ orensson Cadence Berkeley Labs, Berkeley, USA. EECS Department, University of California, Berkeley, USA. Chalmers University of Technol Add to Reading List Source URL: www.bvsrc.org Download Document from Source Website File Size: 192,12 KB Share Document on Facebook

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