Cache control instruction - PDFSEARCH.IO - Document Search Engine

Cache control instruction
Results: 13

#	Item
1	Godson-2E software manual Contents 1 Godson-2E Micro Architecture...................................................................................1 1.1 Godson Series Processors ........................................ Add to Reading List Source URL: dev.lemote.com Language: English - Date: 2011-05-04 12:04:52 Central processing unit CPU cache Translation lookaside buffer Loongson Processor register Control register Instruction set Addressing mode MIPS instruction set Draft:Cache memory
2	Cache Refill/Access Decoupling for Vector Machines Christopher Batten, Ronny Krashinsky, Steve Gerding, Krste Asanović Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology Add to Reading List Source URL: www.lcs.mit.edu Language: English - Date: 2004-11-20 00:25:45 Computing Parallel computing Computer architecture Central processing unit Computer hardware Data parallelism Cache control instruction
3	D Intel® XScale™ Microarchitecture Technical Summary Product Features Add to Reading List Source URL: www.a4com.de Language: English - Date: 2006-12-21 09:47:13 Computing ARM architecture XScale Control register CPU cache Microarchitecture Instruction set Processor register Comparison of CPU architectures Computer architecture Computer hardware Central processing unit
4	Alpha[removed]Microprocessor Data Sheet Order Number: EC–QAEPD–TE Revision/Update Information: Digital Equipment Corporation Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:36 Computing DEC Alpha PALcode Control register CPU cache Joint Test Action Group Alpha 21164 Instruction set Translation lookaside buffer Computer architecture Computer hardware Central processing unit
5	TX System RISC TX79 Core Architecture (Symmetric 2-way superscalar 64-bit CPU) Rev. 2.0 The information contained herein is subject to change without notice. Add to Reading List Source URL: www.lukasz.dk Language: English - Date: 2011-04-11 16:54:05 Computing Control register MIPS architecture Processor register Program counter CPU cache Reduced instruction set computing Instruction set Classic RISC pipeline Computer architecture Central processing unit Computer hardware
6	Tech. Rep[removed]Scalability of Atomic Primitives on Distributed Shared Memory Multiprocessors Maged M. Michael Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2011-03-27 21:03:43 Compare-and-swap Linearizability Test-and-set Fetch-and-add Non-blocking algorithm CPU cache Spinlock Parallel computing Instruction set Concurrency control Computing Computer architecture
7	Location-Based Memory Fences Edya Ladan-Mozes I-Ting Angelina Lee Dmitry Vyukov∗ Add to Reading List Source URL: people.csail.mit.edu Language: English - Date: 2011-05-12 16:11:00 Central processing unit Computer memory Concurrency control Instruction set architectures Memory barrier CPU cache Parallel computing Linearizability Microarchitecture Computer architecture Computing Computer hardware
8	Location-Based Memory Fences Edya Ladan-Mozes I-Ting Angelina Lee Dmitry Vyukov∗ Add to Reading List Source URL: supertech.csail.mit.edu Language: English - Date: 2014-09-16 08:27:50 Computer memory Central processing unit Concurrency control Instruction set architectures CPU cache Memory barrier Parallel computing Linearizability Cache Computer architecture Computing Computer hardware
9	Preliminary Information — Subject to Change Advanced Synchronization Add to Reading List Source URL: developer.amd.com Language: English - Date: 2013-10-24 18:18:04 Computer memory X86 architecture Central processing unit Instruction set architectures X86 Double compare-and-swap MOV Memory barrier CPU cache Computer architecture Computing Concurrency control
10	PDF Document Add to Reading List Source URL: stuff.mit.edu Language: English - Date: 1996-10-15 06:55:03 Central processing unit Programming idioms Assembly languages Machine code Instruction set architectures X86 debug register Control register Addressing mode CPU cache Computer architecture Computing Computer hardware