Preliminary AN1013 SigmaQuad Separate I O Design Guide Introduction - Delay-locked loop - Document - PDFSEARCH.IO

First Page		Document Content
Date: 2013-12-10 07:45:29 Computer hardware Sigmaquad Flip-flop Clock signal Delay-locked loop Quad Data Rate SRAM Synchronous dynamic random-access memory Computer memory Electronic engineering Electronics		Preliminary AN1013 SigmaQuad Separate I/O Design Guide Introduction Add to Reading List Source URL: www.gsitechnology.com Download Document from Source Website File Size: 475,82 KB Share Document on Facebook

	614 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 4, APRIL 2003 Jitter Transfer Characteristics of Delay-Locked Loops—Theories and Design Techniques DocID: 14toQ - View Document
	NETWORKS Principles of Robust Timing over the Internet The key to synchronizing clocks over networks is taming delay variability. Julien Ridoux and Darryl Veitch, University of Melbourne DocID: 14iRW - View Document
	1804 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002 A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly DocID: 13R5N - View Document
	[removed]On-Board Data Processing Part Time-Comparison-Equipment Processing Unit (TCE-PRO) KIUCHI Hitoshi, IMAE Michito, TAKAHASHI Yasuhiro, GOTOH Tadahiro, NAKAGAWA Fumimaru, FUJIEDA Miho, and HOSOKAWA Mizuhiko In satelli DocID: XWUa - View Document
	Systems Involving Group Delay DocID: 9ZjV - View Document