![Digital electronics / Electrical circuits / Diagrams / And-inverter graph / Field-programmable gate array / Static timing analysis / Propagation delay / Logic synthesis / Retiming / Electronic engineering / Electronic design automation / Formal methods Digital electronics / Electrical circuits / Diagrams / And-inverter graph / Field-programmable gate array / Static timing analysis / Propagation delay / Logic synthesis / Retiming / Electronic engineering / Electronic design automation / Formal methods](https://www.pdfsearch.io/img/8a1eeb395a3a2c640cc969ec701191e1.jpg) Date: 2008-09-11 21:52:58Digital electronics Electrical circuits Diagrams And-inverter graph Field-programmable gate array Static timing analysis Propagation delay Logic synthesis Retiming Electronic engineering Electronic design automation Formal methods | | Global Delay Optimization using Structural Choices Abstract This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mappeAdd to Reading ListSource URL: www.bvsrc.orgDownload Document from Source Website File Size: 104,70 KBShare Document on Facebook
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