Global Delay Optimization using Structural Choices Abstract This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mappe - Electrical circuits - Document - PDFSEARCH.IO

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	Global Delay Optimization using Structural Choices Abstract This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mappe Add to Reading List Document Date: 2008-09-11 21:52:58 Open Document File Size: 104,70 KB Share Result on Facebook Company ABC / Intel / / Facility LUT library / / IndustryTerm Structural technology / technology mapping several times / large networks / delay-optimization algorithm / technology mapping algorithm / technology independent algorithms / baseline technology / technology mapping program / technology-independent logic network / particular technology / technology mapping / technology mapper / proposed delay-optimization algorithm / technology dependent synthesis / recent algorithms / / Person C. L. Berman / A. Kuehlmann / V / / Position representative / D. J. / / Technology baseline technology / FPGA / RAM / 3 Proposed algorithm / 1 Introduction Technology / proposed algorithm / technology mapping algorithm / retiming-based technology mapping algorithm / particular technology / CAD / delay-optimization algorithm / proposed delay-optimization algorithm / / URL http / SocialTag Digital electronics Electrical circuits Diagrams And-inverter graph Field-programmable gate array Static timing analysis Propagation delay Logic synthesis Retiming Electronic engineering

Global Delay Optimization using Structural Choices Abstract This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mappeAdd to Reading List