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Formal methods / Electronic design automation / Field-programmable gate array / Statistical static timing analysis / Static timing analysis / Standard cell / Application-specific integrated circuit / Integrated circuit design / Pattern matching / Electronic engineering / Electronics / Integrated circuits


Accelerating Monte Carlo based SSTA Using FPGA Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan and Yi Zou Computer Science Department, University of California, Los Angeles Los Angeles, CA 9009
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Document Date: 2010-02-11 21:54:56


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File Size: 181,08 KB

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