Joel Emer

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1	Adaptive Insertion Policies for High Performance Caching Moinuddin K. Qureshi† Aamer Jaleel§ Yale N. Patt† Simon C. Steely Jr.§ Joel Emer§ †ECE Department The University of Texas at Austin {moin, Add to Reading List Source URL: researcher.watson.ibm.com Language: English - Date: 2010-10-27 12:12:26 Virtual memory Cache Computing Software Computer architecture Cache algorithms CPU cache Adaptive replacement cache Thrashing Working set Paging Pseudo-LRU
2	Late-Binding: Enabling Unordered Load-Store Queues Franziska Roesner x Simha Sethumadhavan x y x Joel S. Emer Add to Reading List Source URL: www.franziroesner.com Language: English - Date: 2009-10-21 14:03:34 Central processing unit Memory disambiguation CPU cache Microarchitecture Hazard Branch predictor Processor register Out-of-order execution DEC Alpha Computer architecture Computer hardware Computer engineering
3	Guest Editor’s Introduction MICRO’S TOP PICKS FROM MICROARCHITECTURE CONFERENCES Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 00:20:11 Josep Torrellas International nongovernmental organizations Wen-mei Hwu Tom Conte Institute of Electrical and Electronics Engineers Joel Emer Intel University of Illinois at Urbana–Champaign Champaign County Illinois Computing Academia