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Electronic design automation / Multiple patterning / Extreme ultraviolet lithography / 32 nanometer / 65 nanometer / Standard cell / Photoresist / Photomask / Overlay Control / Microtechnology / Electronic engineering / Materials science


1 Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control Rani S. Ghaida, George Torres, and Puneet Gupta EE Dept., University of California, Los Angeles
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Document Date: 2010-07-29 18:01:55

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File Size: 1,60 MB

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City

Bellingham / /

Company

on Semiconductor / Semiconductor Research Corporation / IEEE Intl / Intel / Semiconductor Manufacturing / /

/

Facility

Cell Library / University of California / C. Poly-line Plus Contacts ST-DPL Standard-Cell Library / /

IndustryTerm

process technologies / metal / double-patterning technology / technology nodes / volume manufacturing / printing / 45nm logic technology / lithography technologies / lithography solution / manufacturing / manufacturing process development / low-volume manufacturing / /

Organization

National Science Foundation / University of California / Los Angeles / /

Person

Rani S. Ghaida / George Torres / Cell / /

Position

Major / controller / /

Product

DPL / /

ProgrammingLanguage

D / BASIC / C++ / /

PublishedMedium

IEEE Transactions on Semiconductor Manufacturing / IEEE Spectrum / /

Technology

one technology / double-patterning technology / ST-DPL technology / double patterning technologies / API / lithography technologies / 45nm logic technology / process technologies / Lithography / process control / /

URL

http /

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