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#	Item
1	Datasheet VCS Functional Verification Choice of Leading SoC Design Teams Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:41:22 Hardware description languages SystemVerilog OpenVera E Functional verification Synopsys Open Verification Methodology Verilog Logic simulation Electronic engineering Electronic design automation Hardware verification languages
2	Synopsys Professional Services Datasheet SoC Integration & Verification At-A-Glance `` Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:40:10 Hillsboro Oregon Synopsys SystemVerilog Physical design Functional verification E OpenVera Virtual Socket Interface Alliance Electronic engineering Electronic design automation Hardware verification languages
3	[removed]DZ[removed]PrepressPdfNoBL.pdf Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-24 17:15:57 Hardware verification languages Synopsys Integrated circuit design Electronic design automation OpenVera SystemVerilog Physical design Application-specific integrated circuit Design closure Electronic engineering Electronic design Integrated circuits
4	Microsoft Word[removed]3_10-K as printed 2005.doc Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-24 17:15:57 Integrated circuits Hardware verification languages Synopsys Integrated circuit design Signoff Physical design OpenVera Design rule checking SystemVerilog Electronic engineering Electronic design automation Electronic design
5	Synopsys Professional Services Datasheet SoC Integration & Verification At-A-Glance `` Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 12:40:10 Hillsboro Oregon Synopsys SystemVerilog Physical design Functional verification E OpenVera Virtual Socket Interface Alliance Electronic engineering Electronic design automation Hardware verification languages
6	Datasheet VCS Functional Verification Choice of Leading SoC Design Teams Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:41:22 Hardware description languages SystemVerilog OpenVera E Functional verification Synopsys Open Verification Methodology Verilog Logic simulation Electronic engineering Electronic design automation Hardware verification languages

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