| Document Date: 2014-09-09 10:48:46
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Company Host CPU Comp. / Host / Kalray / Kahn Process Networks / / / Event Company Expansion / / Facility library GCC / Subgraph bar Fig / / IndustryTerm source-to-source compilation chain / elementary image analysis operators / energy consumption / image processing application / Experiments show lowest energy consumption / energy-efficiency / parallel hardware / energy performance results / overall compilation chain / Typical applications / manycore chip / dedicated software interface / target hardware / image processing / embedded applications / parallel processing power / low energy consumption / slower operators / compilation chain / image applications / image analysis applications / inter-cluster communications / external communications / software targets / compiler chain / streaming image operators / test applications / test case applications / image processing applications / / Person Synchronous DataFlow / Pierre Guillou / François Irigoin / Fabien Coelho / / Position model / TSAR / / Product DAGs / MPPA-256 chip / Kalray MPPA-256 / / ProgrammingLanguage C / / ProvinceOrState Manitoba / / Technology Ethernet / FPGA / manycore chip / RAM / host processor / real-time Operating System / 28 nm System-on-Chip / MPPA-256 processor / MPPA processor / MPPA-256 chip / API / MPPA chip / high-speed toroidal Network-on-Chip / Image Processing / parallel processing / /
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Automatic Streamization of Image Processing Applications Pierre Guillou, Fabien Coelho, and François Irigoin MINES ParisTech, PSL Research University