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|---|---|---|
 Date: 2012-06-23 07:08:32Electromagnetism Clock distribution network Integrated circuit design Clock Central processing unit Azuro Clock gating Clock signal Electronic engineering Electronics |
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[removed]Cyclos Power Performance Conundrum White Paper[2] | Power Reduction Through RTL Clock Gating By Frank Emnett and Mark Biegel Automotive Integrated Electronics CorporationDocID: 1sYa9 - View Document |
| IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 4, APRILDesign Flow for Flip-Flop Grouping in Data-Driven Clock GatingDocID: 1loEA - View Document |
| Temperature-Aware GPU Design Jeremy W. Sheaffer, Kevin Skadron, and David P. Luebke University of Virginia Dept. of Computer Science {jws9c, skadron, luebke}@cs.virginia.edu The Need for Temperature-Aware DesignDocID: 1geTg - View Document |
| A10 SO nly Allwinner Technology CO., Ltd.DocID: 1aPJz - View Document |
| Datasheet Power Compiler Power Optimization in Design Compiler OverviewDocID: 15bD2 - View Document |