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Digital electronics / Electronic design / And-inverter graph / Field-programmable gate array / Logic synthesis / Static timing analysis / Placement / Logic optimization / Propagation delay / Electronic engineering / Electronic design automation / Formal methods


Microsoft Word - fpga061s-mishchenko1.doc
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Document Date: 2009-12-16 19:04:56

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File Size: 218,08 KB

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City

Monterey / /

Company

IBM / Synopsys / Mentor Graphics / ABC / Altera / Xilinx / Intel / Actel / /

Country

United States / /

Currency

USD / /

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Facility

LUT library / EECS University of California / /

IndustryTerm

logic network / delay-optimization algorithm / technology independent algorithms / particular technology / technology mapping / proposed delay-optimization algorithm / depth-optimal area optimization mapping algorithms / technology mapping several times / large networks / technology mapping algorithm / baseline technology / technology mapping program / technology mapper / technology dependent synthesis / /

Organization

National Science Foundation / University of California / Berkeley / /

Person

C. L. Berman / Lev Delay / A. Kuehlmann / V / Stephen Jang / /

Position

representative / General / D. J. / /

ProvinceOrState

California / /

Technology

baseline technology / FPGA / RAM / area optimization mapping algorithms / proposed algorithm / INTRODUCTION Technology / particular technology / Structural FPGA technology / proposed delay-optimization algorithm / SRAM / technology mapping algorithm / retiming-based technology mapping algorithm / Integrated Circuits / CAD / delay-optimization algorithm / /

URL

http /

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