Drain-induced barrier lowering

Results: 15



#Item
12015 20th IEEE European Test Symposium (ETS)  ! New Drain Current Model for Nano-Meter MOS Transistors On-Chip Threshold Voltage Test

2015 20th IEEE European Test Symposium (ETS) ! New Drain Current Model for Nano-Meter MOS Transistors On-Chip Threshold Voltage Test

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Source URL: www.ridgetopgroup.com

Language: English - Date: 2015-08-06 17:54:54
2Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal Mapping Techniques T. A. Fjeldly *, S. Kolberg* and B. Iñiguez** *  UniK – University Graduate Center, Norwegian University of Science and Technol

Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal Mapping Techniques T. A. Fjeldly *, S. Kolberg* and B. Iñiguez** * UniK – University Graduate Center, Norwegian University of Science and Technol

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Source URL: www.nsti.org

Language: English - Date: 2012-06-27 17:07:44
3Compact model for ultra-short channel four-terminal DG MOSFETs for exploring circuit characteristics T. Nakagawa*, T. Sekigawa*, T. Tsutsumi**, M. Hioki*, E. Suzuki*, and H. Koike* *  Electroinformatics Group,

Compact model for ultra-short channel four-terminal DG MOSFETs for exploring circuit characteristics T. Nakagawa*, T. Sekigawa*, T. Tsutsumi**, M. Hioki*, E. Suzuki*, and H. Koike* * Electroinformatics Group,

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Source URL: www.nsti.org

Language: English - Date: 2011-11-18 13:54:24
4A computationally efficient method for analytical calculation of potentials in undoped symmetric DG SOI MOSFET Oana Cobianu * and Manfred Glesner** Institute of Microelectronic Systems, Darmstadt University of Technology

A computationally efficient method for analytical calculation of potentials in undoped symmetric DG SOI MOSFET Oana Cobianu * and Manfred Glesner** Institute of Microelectronic Systems, Darmstadt University of Technology

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Source URL: www.nsti.org

Language: English - Date: 2012-06-27 17:11:59
5Spectra Journal_FINAL.pdf

Spectra Journal_FINAL.pdf

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Source URL: www.seas.virginia.edu

Language: English - Date: 2014-04-04 11:55:04
6IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 10, OCTOBER[removed]A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 10, OCTOBER[removed]A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold

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Source URL: www.async.caltech.edu

Language: English - Date: 2014-09-24 17:59:20
7

PDF Document

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Source URL: www.nsti.org

Language: English - Date: 2006-06-09 07:22:26
8

PDF Document

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Source URL: www.nsti.org

Language: English - Date: 2006-06-09 07:22:03
9A Unified Process-Based Compact Model for Scaled PD/SOI and Bulk-Si MOSFETs Jerry G. Fossum University of Florida Gainesville, FL[removed]http://www.soi.tec.ufl.edu)

A Unified Process-Based Compact Model for Scaled PD/SOI and Bulk-Si MOSFETs Jerry G. Fossum University of Florida Gainesville, FL[removed]http://www.soi.tec.ufl.edu)

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Source URL: www.nsti.org

Language: English - Date: 2010-03-19 15:18:44
10Present Status and Future Direction of BSIM SOI Model for High Performance/Low-Power/RF Application Samuel K. H. Fung, *Pin Su, *Wan Hui, *Chenming Hu IBM Microelectronics, Semiconductor Research and Development Center (

Present Status and Future Direction of BSIM SOI Model for High Performance/Low-Power/RF Application Samuel K. H. Fung, *Pin Su, *Wan Hui, *Chenming Hu IBM Microelectronics, Semiconductor Research and Development Center (

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Source URL: www.nsti.org

Language: English - Date: 2010-03-19 15:20:38