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Technology / MOSFET / Drain Induced Barrier Lowering / Silicon-germanium / Field-effect transistor / Bipolar junction transistor / IC power supply pin / Threshold voltage / Transistor model / Integrated circuits / Electrical engineering / Electronic engineering
Date: 2010-03-19 15:18:44
Technology
MOSFET
Drain Induced Barrier Lowering
Silicon-germanium
Field-effect transistor
Bipolar junction transistor
IC power supply pin
Threshold voltage
Transistor model
Integrated circuits
Electrical engineering
Electronic engineering

A Unified Process-Based Compact Model for Scaled PD/SOI and Bulk-Si MOSFETs Jerry G. Fossum University of Florida Gainesville, FL[removed]http://www.soi.tec.ufl.edu)

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