![Technology / MOSFET / Drain Induced Barrier Lowering / Silicon-germanium / Field-effect transistor / Bipolar junction transistor / IC power supply pin / Threshold voltage / Transistor model / Integrated circuits / Electrical engineering / Electronic engineering Technology / MOSFET / Drain Induced Barrier Lowering / Silicon-germanium / Field-effect transistor / Bipolar junction transistor / IC power supply pin / Threshold voltage / Transistor model / Integrated circuits / Electrical engineering / Electronic engineering](https://www.pdfsearch.io/img/7ed4f7525214e513ca727edbc1a810b7.jpg) Date: 2010-03-19 15:18:44Technology MOSFET Drain Induced Barrier Lowering Silicon-germanium Field-effect transistor Bipolar junction transistor IC power supply pin Threshold voltage Transistor model Integrated circuits Electrical engineering Electronic engineering | | A Unified Process-Based Compact Model for Scaled PD/SOI and Bulk-Si MOSFETs Jerry G. Fossum University of Florida Gainesville, FL[removed]http://www.soi.tec.ufl.edu)Add to Reading ListSource URL: www.nsti.orgDownload Document from Source Website File Size: 181,78 KBShare Document on Facebook
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