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Retiming
Results: 32

#	Item
21	Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Jie-Hong Jiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-05-01 15:17:53 Digital electronics Electronic design And-inverter graph Retiming Logic synthesis Algorithm Field-programmable gate array Logic gate Parallel computing Electronic engineering Electronic design automation Formal methods
22	Scalable and Scalably-Verifiable Sequential Synthesis Alan Mishchenko Michael Case Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-07-28 20:26:28 Electronic design automation Electrical circuits And-inverter graph Diagrams Retiming Automatic test pattern generation Scan chain Combinational logic Sequential logic Electronic engineering Formal methods Digital electronics
23	Combinational and Sequential Mapping with Priority Cuts Alan Mishchenko Sungmin Cho Satrajit Chatterjee Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-08-14 15:34:24 Electrical engineering And-inverter graph Diagrams Electronic design automation Search algorithms Retiming Field-programmable gate array Directed acyclic graph A* search algorithm Electronic engineering Formal methods Graph theory
24	Magic: An Industrial-Strength Logic Optimization, Technology Mapping, and Formal Verification System Alan Mishchenko Niklas Een Robert Brayton Stephen Jang Maciej Ciesielski Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2010-03-19 22:25:46 Digital electronics Integrated circuits Standard cell Field-programmable gate array Logic optimization Retiming Physical design Logic synthesis Placement Electronic engineering Electronic design automation Electronic design
25	Invariant-Strengthened Elimination of Dependent State Elements Michael L. Case1,2 Alan Mishchenko1 1 Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-05-19 21:42:19 Mathematics Electronics And-inverter graph Diagrams Retiming Invariant Logic synthesis Directed acyclic graph Functional dependency Electronic engineering Formal methods Electronic design automation
26	New Traffic Safety Grants Available! PROGRAM ELIGIBLE PROJECTS Study and Removal of Unwarranted Traffic Signals Traffic Signal Retiming Development of Detour, Special Add to Reading List Source URL: www.rve.com Language: English - Date: 2015-01-12 10:03:26 Road transport Traffic signals Road safety Traffic light Pennsylvania Department of Transportation Traffic Transport Land transport Traffic law
27	ADAPTIVE SIGNAL CONTROL TECHNOLOGY OVERVIEW Eddie Curtis, P.E. FHWA Resource Center Agenda Add to Reading List Source URL: www.fhwa.dot.gov Language: English - Date: 2013-08-14 10:14:30 Retiming Traffic light Traffic signals Signal timing Alpharetta Georgia
28	1 Slack Matching Quasi Delay-Insensitive Circuits Piyush Prakash, Alain J. Martin Department of Computer Science California Institute of Technology Add to Reading List Source URL: www.async.caltech.edu Language: English - Date: 2006-12-08 14:20:38 Graph theory Convex optimization Linear programming Operations research Matching Retiming Graph Mathematics Theoretical computer science Applied mathematics
29	Datasheet DC Ultra Concurrent Timing, Area, Power and Test Optimization Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-03-19 18:15:41 Logic synthesis Physical design High-level synthesis Register-transfer level Placement Quality of results Multi-core processor Synopsys Retiming Electronic engineering Electronic design automation Electronics
30	Post-placement C-slow Retiming for the Xilinx Virtex FPGA Add to Reading List Source URL: www.cs.york.ac.uk Language: English - Date: 2005-10-26 10:32:47 Digital electronics Electronic design C-slowing Formal methods Retiming Field-programmable gate array Xilinx Flip-flop LEON Electronic engineering Electronics Electronic design automation