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#	Item
71	Programming and Debugging Shared Memory Programs with Data Coloring Luis Ceze† , Christoph von Praun‡ , C˘alin Ca¸scaval‡ Pablo Montesinos# and Josep Torrellas# † Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2009-02-28 21:02:25 Data Computing Transactional memory Linearizability Software transactional memory Parallel computing Lock Consistency model Atomicity Transaction processing Concurrency control Data management
72	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction Luis Ceze, Karin Strauss, James Tuck, Jose Renau† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, kstrauss, jtuck, torrellas}@c Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2004-12-21 00:54:20 Central processing unit Runahead CPU cache Microprocessors Branch predictor Memory-level parallelism Microarchitecture Instruction window Hardware scout Computer architecture Computer hardware Computer engineering
73	do i:[removed][removed] Two Hardware-Based Approaches for Deterministic Multiprocessor Replay By Derek R. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, and Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-26 23:39:42 Central processing unit Parallel computing Chunk Process CPU cache Computer architecture Computing Computer hardware Computer memory
74	Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation∗ Jose Renau† James Tuck Wei Liu Luis Ceze Karin Strauss Josep Torrellas † Dept. of Computer Engineering, University of Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-09-06 12:30:36 Central processing unit Parallel computing Classes of computers Microprocessors Superscalar Microarchitecture Speculative multithreading SPECint Coprocessor Computing Computer hardware Computer architecture
75	Colorama: Architectural Support for Data-Centric Synchronization ∗ Luis Ceze, Pablo Montesinos, Christoph von Praun† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, pmontesi, torrellas}@cs.u Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-12-17 12:19:01 Computer programming Critical section Lock Subroutine Linearizability Pointer Mutual exclusion Parallel computing Monitor Computing Concurrency control Software engineering
76	CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses LUIS CEZE, KARIN STRAUSS, JAMES TUCK, and JOSEP TORRELLAS University of Illinois at Urbana–Champaign and JOSE RENAU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 00:10:17 Central processing unit Computer memory Runahead Cache CPU cache Branch predictor Microarchitecture Memory hierarchy Speculative execution Computer architecture Computer hardware Computer engineering
77	SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas CESR, NC State University [removed] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-23 23:23:55 Cryptography Debugging C Software bug Software testing Digital signature Computing Software engineering Computer programming
78 $Colorama: Architectural Support for DataCentric Synchronization Luis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas PHJVTH NYV\W$	Colorama: Architectural Support for DataCentric Synchronization Luis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas PHJVTH NYV\W Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-24 11:54:30 Lock Palette Concurrency control Critical section Computing
79	DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently∗ Pablo Montesinos, Luis Ceze† and Josep Torrellas Department of Computer Science University of Illinois at Urbana Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:04:57 Central processing unit Chunk CPU cache Parallel computing C dynamic memory allocation Computer memory Computing Computer hardware
80	BulkSC: Bulk Enforcement of Sequential Consistency Luis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-24 00:13:26 Sequential consistency Josep Torrellas Transaction processing Consistency model Computing