<--- Back to Details
| First Page | Document Content | |
|---|---|---|
 Date: 2006-05-01 16:05:11Digital electronics Electronic design Formal methods And-inverter graph Retiming Logic synthesis Automatic test pattern generation Field-programmable gate array Sequential logic Electronic engineering Electronics Electronic design automation |
Add to Reading List |
Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Robert Brayton | Microsoft Word - speedup10.docDocID: O7jr - View Document |
 | Scalable Logic Synthesis using a Simple Circuit Structure Alan Mishchenko Robert Brayton EECS Department, University of California, Berkeley, CA 94720DocID: O4NK - View Document |
 | Microsoft Word - power18.docDocID: O4L0 - View Document |
 | Verification after Synthesis Alan Mishchenko Robert Brayton Department of EECSDocID: O4H3 - View Document |
| Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Robert BraytonDocID: O3JU - View Document |